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Ordering number : ENN*6692
CMOS IC
LC86P7148
8-Bit Single Chip Microcontroller with One-Time Programmable PROM
Preliminary Overview
The LC86P7148 is a CMOS 8-bit single chip microcontroller with one-time PROM for the LC867100 series. This microcontroller has the function and the pin description of the LC867100 series mask ROM version, and 48K-byte PROM. QFP package are available for shipping as well as LC867100 series. It is suitable to set up first release, prototyping, developing and testing of set.
Features
(1) Option switching by PROM data The option function of the LC867100 series can be specified by the PROM data. LC86P7148 can be checked the functions of the trial pieces using the mass production board. (2) Internal one-time PROM capacity : 49152 bytes (3) Internal RAM capacity : 1152 bytes Used PROM or RAM capacity are equal ROM or RAM capacity of mask ROM version which applies LC86P7148. Mask ROM version LC867148 LC867140 LC867132 LC867128 LC867124 LC867120 LC867116 LC867112 LC867108 PROM capacity 49152 bytes 40960 bytes 32768 bytes 28672 bytes 24576 bytes 20480 bytes 16384 bytes 12288 bytes 8192 bytes RAM capacity 1152 bytes 1152 bytes 768 bytes 768 bytes 768 bytes 640 bytes 640 bytes 512 bytes 512 bytes
Programming service
We offers various services at nominal charges. These include the ROM writing, the ROM reading, the package stamping and the screening. Contact our representative for further information.
Ver.1.00 D2994
91400 RM (IM) HK No.6692-1/21
LC86P7148 (4) Operating supply voltage : 4.5V to 6.0V (5) Instruction cycle time : 1s to 366s (6) Operating temperature : -30C to +70C (7) The pin compatible with the LC867100 series mask ROM devices (8) Applicable mask ROM version : LC867148/LC867140/LC867132/LC867128/LC867124/LC867120 /LC867116/LC867112/LC867108 (9) Factory shipment : QFP80E
Notice for use
LC86P7148 is provided for the first release and small shipping of the LC867100 series. At using, take notice of the followings. (1) A point of difference LC86P7148 and LC867100 series Item LC86P7148 LC867148/40/32/28/24/20/16/12/08 Operation after reset The option is specified until 3ms after going The program is executed from 00H of the releasing to a `H' level to the reset terminal by program counter immediately after going to degrees. The program is executed from 00H a `H' level to the reset terminal. of the program counter. Operating supply 4.5V to 6.0V 2.5V to 6.0V voltage range (VDD) Total output current Refer to `electrical characteristics' on the semiconductor news. [IOAL(2)] [IOAL(3)] Power dessipation LC86P7148 uses 256 bytes that is addressed on 0FF00H to FFFFH in the program memory as the option configuration data area. This option configuration can execute all options which LC867100 series have. Next tables show the options that correspond and not correspond to LC86P7148. * A kind of the option corresponding of the LC86P7148 A kind of option Pins, Circuits Input/output form of Port 0 input/output ports (specified in a bit)
Port 1 (specified in a bit) *1 Port 7 (specified in a bit) *1 Each of P74 and P75 has no option
Pull-up MOS Tr. of input port
Contents of the option 1. Input : No Pull-up MOS Tr. Output : N-channel open drain *1 2. Input : Pull-up MOS Tr. Output : CMOS *2 1. Input : Programmable pull-up MOS Tr. Output: N-channel open drain 2. Input : Programmable pull-up MOS Tr. Output : CMOS 1. No Pull-up MOS Tr. 2. Pull-up MOS Tr.
*1) Specified in a bit. *2) Specified in nibble unit.
Pull-up MOS Tr. is not provided in N-channel open drain output port.
No.6692-2/21
LC86P7148 (2) Option The option data is created by the option specified program "SU86K.EXE". program area by linkage loader "L86K.EXE". The created option data is linked to the
(3) ROM space LC86P7148 and LC867100 series use 256 bytes that is addressed on 0FF00H to 0FFFFH in the program memory as the option specified data area. These program memory capacity are 49152 bytes that is addressed on 0000H to 0BFFFH.
0FFFFH 0FF00H 0EFFFH 0DFFFH 0CFFFH 0BFFFH 0AFFFH 9FFFH 8FFFH 7FFFH 6FFFH 5FFFH 4FFFH 3FFFH 2FFFH 1FFFH 0FFFH 0000H
Option data area 256 bytes
Option Data Area
Option Data Area
Option Data Area
Option Data Area
Program area 48K bytes LC867148
Program area 40K bytes LC867140
Program area 32K bytes LC867132
Program area 28K bytes LC867128
Program area 24K bytes LC867124
0FFFFH 0FF00H 0EFFFH 0DFFFH 0CFFFH 0BFFFH 0AFFFH 9FFFH 8FFFH 7FFFH 6FFFH 5FFFH 4FFFH 3FFFH 2FFFH 1FFFH 0FFFH 0000H
Option data area 256 bytes
Option Data Area
Option Data Area
Option Data Area
Program area 20K bytes LC867120
Program area 16K bytes LC867116
Program area 12K bytes LC867112
Program area 8K bytes LC867108
(4) Ordering information 1. When ordering the identical mask ROM and PROM devices simultaneously. Provide an EPROM containing the target memory contents together with the separate order forms for each of the mask ROM and PROM versions. 2. When ordering a PROM device. Provide an EPROM containing the target memory contents together with an order form.
No.6692-3/21
LC86P7148
How to use
(1) Specification of option The LC86P7148 must be programmed after specifying option data. The option is specified by "SU86K.EXE". The specified option file and the file created by our macro assembler "M86K.EXE" are linked by our linkage loader "L86K.EXE" which creates .HEX file, then the option code is put in the option specified area (0FF00H to 0FFFFH) of its .HEX file. (2) How to program for the EPROM The LC86P7148 can be programmed by EPROM programmer with attachment ; W86EP7148Q * Recommended EPROM programmer Productor Advantest Andou AVAL Minato electronics EPROM programmer R4945, R4944, R4943 AF-9704 PKW-1100, PKW-3000 MODEL1890A The address must be set to "0 to 0FFFFH" and a
* "27512 (Vpp=12.5V) Intel high speed programming" mode available. jumper (DASEC) must be set to `OFF' at programming.
(3) How to use the data security function "Data security" is the disabled function to read the data of the EPROM. The following is the process in order to execute the data security. 1. Set `ON' the jumper of attachment. 2. Program again. Then EPROM programmer displays the error. The error means normally activity of the data security. It is not a trouble of the EPROM programmer or the LSI. Notes * Data security is not executed when the data of all address have `FFH' at the sequence 2 above. * The programming by a sequential operation "BLANK=>PROGRAM=>VERIFY" cannot be executed data security at the sequence 2 above. * Set to `OFF' the jumper after executing the data security.
Data security
Not data security
W86EP7148Q
No.6692-4/21
LC86P7148
Pin Assignment
COM0/PL0 V1/PL4 V2/PL5 V3/PL6 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 S23/PC7 S22/PC6 S21/PC5 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S13/PB5 S12/PB4 VSS3 VDD3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Package Dimension (unit : mm)
3174
P13/SO1 P14/SI1/SB1 P15/SCK1 P16/BUZ P17/PWM0 P70/INT0 RES XT1/P74 XT2/P75 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P90/DA0/AN8 P91/DA1/AN9 P92/DA2/AN10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
COM1/PL1 COM2/PL2 COM3/PL3 VSS2 VDD2 P00 P01 P02 P03 P04 P05 P06 P07 P10/SO0 P11/SI0/SB0 P12/SCK0
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 S0/PA0 P73/INT3/T0IN P72/INT2/T0IN P71/INT1 P93/DA3/AN11
SANYO : QIP-80E
Notes *The QFP packages should be heat-soaked for 12 hours at 125C immediately prior to mounting (This baking is called pre-baking). *After pre-baking a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30C or less and a humidity level of 70% or less. Please solder within 24 hours.
No.6692-5/21
LC86P7148
System Block Diagram
Interrupt Control
IR
PLA A15-A0 D7-D0 TA CE OE DASEC
Stand-by Control
PROM Control
CF Clock Generator RC X'tal PC PROM(48KB)
Base Timer
Bus Interface
ACC
SIO0
Port 1
B Register
SIO1
Port 7
C Register
Timer 0
Port 8 ALU
Timer 1
Port 9
Real Time Service
ADC
PSW
RAM 128 bytes
INT0 - 3 Nose Filter
RAR
LCD Controller
DAC
RAM
S0 - S7 (PA) S8 - S13 (PB) S16 - S23 (PC) S24 - S31 (PD) COM0 - COM3(PL)
Stack Pointer
Port 0
Watchdog Timer
No.6692-6/21
LC86P7148
Pin Description
Pin name VSS1 *1 VSS2 *1 VSS3 *1 VDD1 *1 VDD2 *1 VDD3 *1 PORT0 P00 - P07 I/O I/O Function description Power pin (-) Power pin (-) Power pin (-) Power pin (+) Power pin (+) Power pin (+) * 8-bit input/output port Input/output in nibble units * Input for port 0 interrupt * Input for HOLD release Option * Pull-up resistor : Provided/Not provided (specified in nibble units) * Output form (P00 - P07) : CMOS/N-channel open drain (specified in a bit) * Output form : CMOS/N-channel open drain (specified in a bit) PROM mode
PORT1 P10 - P17
I/O
PORT7 P70 P71 - P73 I/O I
P74 - P75
I
Port8 P80 - P87 PORT9 P90 - P93
I
I/O
* 8-bit input/output port Data line Input/output can be specified in bit unit D0 to D7 * Other pin functions P10 SIO0 data output P11 SIO0 data input/bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input/bus input/output P15 SIO1 clock input/output P16 Buzzer output P17 Timer1 output (PWM output) * 6-bit input port Pull-up resistor : * Other pin functions Power for Provided/Not provided P70 : INT0 input/HOLD release input/ programming (specified in a bit) N-channel Tr. output for watchdog (P70, P71, P72, P73) timer * P74 , P75 don't have the PROM control signals P71 : INT1 input/HOLD release input pull-up resistor option. DASEC(*2) P72 : INT2 input/timer 0 event input P73 : INT3 input with noise filter/timer 0 OE(*3) event input CE(*4) * Interrupt received form, vector address rising falling rising high low vector & level level falling INT0 enable enable disable enable enable 03H INT1 enable enable disable enable enable 0BH INT2 enable enable enable disable disable 13H INT3 enable enable enable disable disable 1BH P74 : XT1 terminal for crystal oscillation P75 : XT2 terminal for crystal oscillation * 8-bit input port * Other function AD input port (8 port pins) * 4-bit input/output port * Other function DA output port (4 port pins) AD input port (4 port pins)
No.6692-7/21
LC86P7148 Pin name PORT A (S0/PA0 - S7/PA7) PORT B (S8/PB0 - S13/PB5) PORT C (S16/PC0 - S23/PC7) I/O I/O Function description * Segment output terminal for LCD display * Can be used as a general input/output port * Segment output terminal for LCD display * Can be used as a general input/output port * Segment output terminal for LCD display * Can be used as a general input/output port Option PROM mode Address input A0 to A7 Address input A8 to A13 PROM control signal input *TA(*5) Address input *A14,A15
I/O
-
I/O
-
* Bias power terminal for LCD drive * Can be used as a general input port I Reset pin RES I * Input pin for 32.768kHz crystal oscillation XT1/ P74 In case of non use, connect to VDD. * Other function A general input port P74 XT2/P75 O * Output pin for 32.768kHz crystal oscillation In case of non use, should be left unconnected ( I ) * Other function A general input port P75 CF1 I Input pin for ceramic resonator oscillation CF2 O Output pin for ceramic resonator oscillation * All of port options can be specified in bit unit except the pull-up resistor of port 0.
PORT D (S24/PD0 - S31/PD7) PORT L (COM0/PL0 - COM3/PL3) V1/PL4 - V3/PL6
I/O
* Segment output terminal for LCD display * Can be used as a general input/output port * Common output terminal for LCD display * Can be used as a general input port
-
I/O
-
I
[Notes] * The VDD1, VDD2 and VDD3 terminals must be shorted electrically each other. * The VSS1, VSS2 and VSS3 terminals must be shorted electrically each other. *1 Connect like the following figure to reduce noise into a VDD terminals.
LSI VDD1
Power Supply
VDD2
VDD3 VSS1 VSS2 VSS3
*2 *3 *4 *5
Memory select input for data security Output enable input Chip enable input TA ! PROM control signal input
No.6692-8/21
LC86P7148 1. Absolute Maximum Ratings at Ta=25C, VSS=VSS1=VSS2=VSS3=0V Ratings typ.
Parameter Supply voltage LCD display voltage Input voltage
Symbol VDDMAX VLCD VI
Pins VDD1, VDD2 VDD3 V1/PL6, V2/PL5 V3/PL4 *Ports 71, 72, 73 *Ports 74, 75 *Port 8, Port L * RES *Ports 0, 1 *Port 9 *Ports A, B, C, D Ports 0, 1 Ports A, B, C, D Port 9 Ports 0, 1 Ports A, B Ports C, D Port 9 Ports 0, 1 Ports A, B, C, D Port 9 Port 70 Ports 0, 1 Ports A, B Ports C, D Port 9 Port 70 QFP80E
Conditions VDD1=VDD2= VDD3 VDD1=VDD2= VDD3
VDD[V]
min. -0.3 -0.3 -0.3
max. +7.0 VDD VDD+0.3
unit V
Input/output voltage High level output current Peak output current Total output current Peak output current Total output current
VIO
-0.3
VDD+0.3
Low level output current
Maximum power dissipation Operating temperature range Storage temperature range
IOPH(1) IOPH(2) IOPH(3) IOAH(1) IOAH(2) IOAH(3) IOAH(4) IOPL(1) IOPL(2) IOPL(3) IOPL(4) IOAL(1) IOAL(2) IOAL(3) IOAL(4) IOAL(5) Pdmax Topr
*CMOS output *At each pins Total all pins Total all pins Total all pins Total all pins At each pins At each pins At each pins At each pins Total all pins Total all pins Total all pins Total all pins Total all pins Ta=-30 to+70C
-4 -4 -4 -30 -20 -20 -20 20 20 20 15 40 24 24 15 10 515 -30 +70
mA
mW C
Tstg
-65
+150
Notes *The QFP packages should be heat-soaked for 12 hours at 125C immediately prior to mounting (This baking is called pre-baking). *After pre-baking a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30C or less and a humidity level of 70% or less. Please solder within 24 hours.
No.6692-9/21
LC86P7148 2. Recommended Operating Range at Ta=-30C to +70C, VSS=VSS1=VSS2=VSS3=0V Ratings typ.
Parameter Operating supply voltage range Hold voltage
Symbol VDD(1) VDD(2) VHD
Pins VDD1,VDD2,VDD3
Conditions 0.98s tCYC 400s 3.9s tCYC 400s RAMs and the registers hold voltage at HOLD mode. Output disable Output disable
VDD[V]
min. 4.5 2.5 2.0
max. 6.0 6.0 6.0
unit V
VDD1,VDD2,VDD3
Input high voltage
VIH(1) VIH(2)
Port 0 *Ports 1, 9 *Ports A, B, C, D *Ports 72, 73 (Schmitt) *Port 70 Port input/interrupt *Port 71 * RES (Schmitt) Port 70 Watchdog timer *Port 8 *Ports 74, 75 Port 0 *Ports 1, 9 *Ports A, B, C, D *Ports 72, 73 (Schmitt) *Port 70 Port input/interrupt *Port 71 * RES (Schmitt) Port 70 Watchdog timer *Port 8 *Ports 74, 75
4.5-6.0 4.5-6.0
0.4VDD
VDD VDD
+0.9 0.75VDD
VIH(3)
Output N-channel Tr. OFF
4.5-6.0
0.75VDD
VDD
VIH(4) VIH(5) Input low voltage VIL(1) VIL(2)
Output N-channel Tr. OFF Using as port Output disable Output disable
4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0
0.9VDD 0.75VDD VSS VSS
VDD VDD 0.2VDD 0.25VDD
VIL(3)
Output N-channel Tr. OFF
4.5-6.0
VSS
0.25VDD
VIL(4) VIL(5) Operation cycle time tCYC
Output N-channel Tr. OFF Using as port
4.5-6.0 4.5-6.0 4.5-6.0
VSS VSS 0.98
0.8VDD
-1.0 0.25VDD 400 s
No.6692-10/21
LC86P7148 Ratings typ. 6
Parameter
Symbol CF1, CF2
Pins
Conditions *6MHz (ceramic resonator oscillation) *Refer to figure 1 *3MHz (ceramic resonator oscillation) *Refer to figure 1 RC oscillation *32.768kHz (crystal oscillation) *Refer to figure 2 *6MHz (ceramic resonator oscillation) *Refer to figure 3 *3MHz (ceramic resonator oscillation) *Refer to figure 3 *32.768kHz (crystal oscillation) *Refer to figure 3
Oscillation FmCF(1) frequency range (Note 1) FmCF(2)
VDD[V] 4.5-6.0
min. 5.88
max. 6.12
unit MHz
CF1, CF2
4.5-6.0
2.94
3
3.06
FmRC FsXtal
XT1, XT2
4.5-6.0 4.5-6.0
0.4
0.8 32.768
3.0 kHz
Oscillation stabilizing time period (Note 1)
tmsCF(1)
CF1, CF2
4.5-6.0
0.05
0.5
ms
tmsCF(2)
CF1, CF2
4.5-6.0
0.10
1.00
tssXtal
XT1, XT2
4.5-6.0
s
(Note 1) The oscillation constant is shown on table 1 and table 2.
No.6692-11/21
LC86P7148 3. Electrical Characteristics at Ta=-30C to +70C, VSS=VSS1=VSS2=VSS3=0V Ratings typ.
Parameter Input high current
Symbol IIH(1)
Pins *Port 1 *Port 0 without pull-up MOS Tr.
Conditions *Output disable *Pull-up MOS Tr. OFF. VIN=VDD (including the offleak current of the output Tr.) VIN=VDD
VDD[V] 4.5-6.0
min.
max. 1
unit A
IIH(2)
IIH(3) IIH(4) IIH(5) IIH(6) Input low current IIL(1)
*Port 7 without pull-up MOS Tr. *Port 8 Port 9 Ports A, B, C, D, L
RES
4.5-6.0
1
Ports 74 ,75 *Port 1 *Port 0 without pull-up MOS Tr.
IIL(2)
IIL(3) IIL(4) IIL(5) IIL(6) Output high voltage VOH(1) VOH(2)
*Port 7 without pull-up MOS Tr. *Port 8 Port 9 Ports A, B, C, D, L
RES
VIN=VDD VIN=VDD VIN=VDD Using as port VIN=VDD *Output disable *Pull-up MOS Tr. OFF. VIN=VSS (including the offleak current of the output Tr.) VIN=VSS
4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 -1
1 1 1 1
4.5-6.0
-1
Ports 74 ,75 Ports 0,1 of CMOS output *Port 9 of CMOS output *Ports A, B, C, D of CMOS output Ports 0, 1 Port 70 Port 9 Ports A, B, C, D of CMOS output
VIN=VSS VIN=VSS VIN=VSS Using as port VIN=VSS IOH=-1.0mA IOH=-1.0mA
4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0
-1 -1 -1 -1 VDD-1 VDD-1 V
Output low voltage
VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7)
IOL=10mA IOL=1.6mA IOL=1mA IOL=6mA IOL=1.2mA IOL=8mA IOL=1.6mA Continue.
4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0
1.5 0.4 0.4 1.5 0.4 1.5 0.4
No.6692-12/21
LC86P7148 Ratings typ.
Parameter LCD output regulation
Symbol VODLS
Pins S0 to S13, S16 to S31
Conditions *Deference voltage to ideal value *VLCD, 2/3VLCD, 1/3VLCD *Deference voltage to ideal value *VLCD, 2/3VLCD, 1/2VLCD, 1/3VLCD Resistance at a ladder resistor *Resistance at a ladder resistor *1/2R mode VOH=0.9VDD
VDD[V] 4.5-6.0
min. 0
max. 0.2
unit V
VODLC
COM0 to COM3
4.5-6.0
0
0.2
LCD ladder resistor
RLCD(1) RLCD(2)
4.5-6.0 4.5-6.0
60 30
k
Pull-up MOS Tr. resistor Hysteresis voltage Pin capacitance
Rpu
VHIS
CP
*Ports 0, 1 *Ports A, B, C, D *Ports 70, 71, 72, 73 *Ports 0, 1 *Ports 70, 71, 72, 73 * RES All pins
4.5-6.0
15
40
70
Output disable
4.5-6.0
0.1VDD
V
*f=1MHz *Unmeasurement terminals for the input are set to VSS level. *Ta=25C
4.5-6.0
10
pF
4. Serial Input/Output Characteristics at Ta=-30C to +70C, VSS=VSS1=VSS2=VSS3=0V Ratings typ.
Parameter Cycle Low Level pulse width High Level pulse width Cycle Low Level pulse width High Level pulse width Data set up time Input clock Output clock
Symbol
Pins
Conditions Refer to figure 5.
tCKCY(1) SCK0, SCK1 tCKL(1) tCKH(1) tCKCY(2) SCK0, SCK1 tCKL(2) tCKH(2) tICK *SI0,SI1 *SB0,SB1
VDD[V] 4.5-6.0 4.5-6.0 4.5-6.0
min. 2 1 1 2
max.
unit tCYC
Serial clock
Data hold time Output delay time (Serial clock is external clock) Output delay time (Serial clock is internal clock)
tCKI tCKO(1) *SO0, SO1 *SB0, SB1
tCKO(2)
*Use pull-up resistor (1k) when open drain output. *Refer to figure 5. *Data set-up to SCK0, 1 *Data hold from SCK0, 1 *Refer to figure 5. *Use pull-up resistor (1k) when open drain output. *Data hold from SCK0, 1 *Refer to figure 5.
4.5-6.0 4.5-6.0 4.5-6.0 4.5-6.0
1/2 tCKCY 1/2 tCKCY 0.1 s
Serial input
4.5-6.0 4.5-6.0
0.1 7/12tCYC +0.2
Serial output
4.5-6.0
1/3tCYC +0.2
No.6692-13/21
LC86P7148 5. Pulse Input Conditions at Ta=-30C to +70C, VSS=VSS1=VSS2=VSS3=0V Ratings typ.
Parameter High/low level pulse width
Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2)
Pins *INT0, INT1 *INT2/T0IN INT3/T0IN (The noise rejection clock is selected to 1/1.) INT3/T0IN (The noise rejection clock is selected to 1/16.) INT3/T0IN (The noise rejection clock is selected to 1/64.)
RES
Conditions *Interrupt acceptable *Timer0-countable *Interrupt acceptable *Timer0-countable
VDD[V] 4.5-6.0 4.5-6.0
min. 1 2
max.
unit tCYC
tPIH(3) tPIL(3)
*Interrupt acceptable *Timer0-countable
4.5-6.0
32
tPIH(4) tPIL(4)
*Interrupt acceptable *Timer0-countable
4.5-6.0
128
tPIL(5)
Reset acceptable
4.5-6.0
200
s
6. AD Converter Characteristics at Ta=-30C to +70C, VSS=VSS1=VSS2=VSS3=0V Ratings typ. 8
Parameter
Symbol
Pins
Conditions
Resolution NAD Absolute precision ETAD (Note 2) Conversion time tCAD
VDD[V] 4.5-6.0 4.5-6.0 4.5-6.0
min.
max. 1.5
unit bit LSB s
AD conversion time = 16 x tCYC (ADCR2=0) (Note 3) AD conversion time = 32 x tCYC (ADCR2=1) (Note 3) AN0 - AN11 VAIN=VDD VAIN=VSS
15.68
(tCYC= 0.98s) 31.36 (tCYC= 0.98s) 4.5-6.0 4.5-6.0 4.5-6.0 VSS
65.28 (tCYC= 4.08s) 130.56 (tCYC= 4.08s) VDD 1
Analog input voltage range Analog port input current
VAIN IAINH IAINL
V A
-1
(Note 2) Absolute precision excepts quantizing error (1/2 LSB). (Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital conversion value to the register.
No.6692-14/21
LC86P7148 7. DA Converter Characteristics at Ta=-30C to +70C, VSS=VSS1=VSS2=VSS3=0V
Ratings typ. 8
Parameter Resolution Total error
Symbol NDA
Pins
Conditions 8 bit mode 9 bit mode 9.5 bit mode (Note 4) 8 bit mode 9 bit mode (1) 9 bit mode (2) 9.5 bit mode (Note 5)
VDD[V] 4.5-6.0 4.5-6.0
min.
max. 1.0 0.8 0.7 0.5 VDD 1/2VDD VDD 2/3VDD
unit bit %
Settling time Analog output voltage range
tSAD VAOUT
DA0 to DA3
4.5-6.0 4.5-6.0
VSS VSS 1/2VDD 1/3VDD 4
s V
Output resistor
RODA
4.5-6.0
k
(Note 4) Settling time means the time from executing the DA conversion instruction to generating the analog voltage output corresponding to the digital data on the specific port. (Note 5) DA data = 80H 8. Current Dissipation Characteristics at Ta=-30C to +70C, VSS=VSS1=VSS2=VSS3=0V
Ratings typ. 15
Parameter Current dissipation during basic operation (Note 6)
Symbol IDDOP(1)
Pins VDD1= VDD2= VDD3
Conditions *FmCF=6MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : CF oscillation *Internal RC oscillation stops *1/1 divided *FmCF=3MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : CF oscillation *Internal RC oscillation stops *1/2 divided *FmCF=0Hz (when oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock : RC oscillation *1/2 divided *FmCF=0Hz (when oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock : crystal oscillation *Internal RC oscillation stops *1/2 divided
VDD[V] 4.5-6.0
min.
max. 30
unit mA
IDDOP(2)
4.5-6.0
6
15
IDDOP(3)
4.5-6.0
4
13
IDDOP(4)
4.5-6.0
4
9
Continue.
No.6692-15/21
LC86P7148
Ratings typ. 6
Parameter
Symbol
Pins VDD1= VDD2= VDD3
Conditions *HALT mode *FmCF=6MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : CF oscillation *Internal RC oscillation stops *1/1 divided *HALT mode *FmCF=3MHz Ceramic resonator oscillation *FsXtal=32.768kHz crystal oscillation *System clock : CF oscillation *Internal RC oscillation stops *1/2 divided *HALT mode FmCF=0Hz (when oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock : RC oscillation *1/2 divided *HALT mode FmCF=0Hz (when oscillation stops) *FsXtal=32.768kHz crystal oscillation *System clock : crystal oscillation *Internal RC oscillation stops *1/2 divided HOLD mode
Current dissipation IDDHALT(1) in HALT mode (Note 6)
VDD[V] 4.5-6.0
min.
max. 11
unit mA
IDDHALT(2)
4.5-6.0
2.2
9
IDDHALT(3)
4.5-6.0
500
1700
A
IDDHALT(4)
4.5-6.0
25
100
IDDHALT(5)
Current dissipation IDDHOLD(1) in HOLD mode (Note 6)
VDD1= VDD2= VDD3
4.5-6.0
0.05
30
(Note 6) The currents of the output transistors and the pull-up MOS transistors are ignored.
No.6692-16/21
LC86P7148 Table 1. Ceramic resonator oscillation recommended constant (main clock) Oscillation type Maker Oscillator C1 C2 6MHz ceramic resonator Murata CSA6.00MG 33pF 33pF oscillation CST6.00MGW on chip KBR-6.0MSA 33pF 33pF Kyocera PBRC6.00A(chip 33pF 33pF type) KBR-6.0MKS on chip PBRC6.00B(chip type) 3MHz ceramic resonator Murata CSA3.00MG 33pF 33pF oscillation CST3.00MGW on chip Kyocera KBR-3.0MS 47pF 47pF * Both C1 and C2 must use K rank (10%) and SL characteristics. Table 2. Crystal oscillation guaranteed constant (sub clock) Maker Oscillator C3 C4
Oscillation type 32.768kHz crystal oscillation
(Notes)
*Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. *If you use other oscillators herein, we provide no guarantee for the characteristics.
CF1
CF2
XT1
XT2
CF C1 C2 C3
X'tal C4
Figure 1
Ceramic oscillation circuit
Figure 2
Crystal oscillation circuit
No.6692-17/21
LC86P7148
VDD Power supply VDD limit 0V Reset time RES
Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2
Operation mode
Unfixed
Reset
Instruction execution mode OCR6=1
Instruction execution mode

HOLD release signal
Valid
Internal RC resonator oscillation CF1, CF2 tmsCF
tssXtal XT1, XT2
Operation mode
HOLD
Instruction execution mode

Figure 3
Oscillation stable time
No.6692-18/21
LC86P7148
VDD
RRES
RES CRES
(Note) Fix the value of CRES, RRES that is sure to reset until 200s, after Power supply has been over inferior limit of supply voltage.
Figure 4
Reset circuit
0.5VDD
tCKCY tCKL SCK0 SCK1 tICK SI0 SI1 tCKO SO0, SO1 SB0, SB1

VDD
tCKH 1k
tCKI
50pF

Figure 5
Serial input / output test condition
tPIL
tPIH
Figure 6
Pulse input timing condition
No.6692-19/21
LC86P7148
Notice for use
* The construction of the one-time programmable microcomputer with a blank built-in PROM makes it impossible for SANYO to completely factory-test it before shipping. To probe reliability of the programmed devices, the screening procedure shown in the following figure should always be followed. * It is not possible to perform a writing test on the blank PROM.. 100% yield, therefore, cannot be guaranteed. * Keeping the dry packing The environment must be held at a temperature of 30C or less and a humidity level of 70% or less. * After opening the packing The preparation procedures shown in the following figure should always be followed prior to mounting the packages on the substrate. Note that the QFP package should be heat-soaked for 12 hours at 125C immediately prior to mounting (This baking is called pre-baking). After pre-baking, a controlled environment must be maintained until soldering. The environment must be held at a temperature of 30C or less and a humidity level of 70% or less. Please solder within 24 hours.
a. Shipping with a blank PROM (Programming the data by yourself)
QFP
b. Shipping with a programmed PROM (Programming the data by Sanyo)
QFP
Writing data for program/Verifying
Baking before mounting 125C, 12 hours Baking
Recommended process of screening Heat-soak 1505C, 24 +1 Hr -0
Mounting Reading ascertain of program VDD=50.5V
Baking before mounting 125C, 12 hours Baking
Mounting
No.6692-20/21
LC86P7148
PS No.6692-21/21

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